On Reducing Glitch Power in Combinational Circuits

In this thesis, first of all, a theoretical framework for dynamic power estimation is presented, in which the concepts of the conventional probabilistic simulation are extended. To cope with the modeling of temporal correlation, an exact glitch-filtering scheme using multidimensional signal probability is proposed within this framework. To compromise the runtime complexity, the exact glitch-filtering scheme is modified. Despite using the modified glitch-filtering scheme, the extended probabilistic simulation is still too slow to be applied to iterative power optimization. To get around time-consuming power estimation, power metric and its calculation method are introduced in this thesis. Based on the power metric, a heuristic gate sizing algorithm for glitch power reduction is proposed. By dividing the search strategy of the proposed gate sizing heuristic into an LP-based global search and a monotonic local search, the basic algorithm can be accelerated by more than 30% for cell-rich standard cell libraries. In addition, three multi-Vt assignment algorithms cooperating with gate sizing are also investigated.